1. Field of the Invention
The present invention relates to a method for designing radiation-hardened programmable devicse such as Field Programmable Gate Arrays (FPGA). More specifically, the present invention relates to circuit designs for a radiation-hardened static random access memory (SRAM) based programmable device.
2. Background
A major concern in building a radiation-hardened SRAM based programmable device such as a FPGA or programmable logic device (PLD) for a space application is the reliability of the configuration memory. Memory devices used in satellites and in other computer equipment, can be placed in environments that are highly susceptible to radiation. A satellite memory cell in a space environment can be exposed to a radiation-induced soft error, commonly called a single event upset (SEU), when a cell is struck by high-energy particles. Electron-hole pairs are created by, and along the path of, a single energetic particle as it passes through an integrated circuit. An SEU typically results from alpha particles (helium nuclei), beta particles or other ionized nuclei impacting a low-capacitance node of a semiconductor circuit. Should the energetic particle generate the critical charge in the critical volume of the memory cell, the logic state of the memory is upset. This critical charge, by definition, is the minimum amount of electrical charge required to change the logic state of the memory cell. It is commonly called Q-Critical (Qcrit).
SEU can change the contents of any volatile memory cell. If that bit of memory is doing something besides merely storing data, such as controlling the logic functionality of an FPGA, or other SRAM-based programmable device the results can be catastrophic. While other technologies may be better suited for the most sensitive control functions of a spacecraft, there is a significant advantage to be had by being able to change a portion of the spacecraft's functionality remotely, either during prototyping on the ground or later during the mission. Spacecraft designers accept the idea that SEUs will inevitably occur. Based on the inevitable, such designers are willing to use SRAM based FPGAs and other programmable devices in non-critical portions of the vehicle provided that the error rate is reasonable, sufficient error trapping is available and the recovery time is reasonable.
When an ion traverses a node within a memory storage cell, the ion can force the node from its original state to an opposite state for a period of time. This change of state is due to the charge that the heavy ion deposits as it passes through the silicon of the metal oxide semiconductor (MOS) transistor of the memory cell. If this node is held in the opposite state for a period of time longer than the delay around the feed back loop of the memory cell, the cell can switch states and the stored data can be lost. The period of time the node is held in the opposite state can depend on several factors, the most critical being the charge deposited.
FIG. 1a is a simplified schematic diagram of a logic gate 104. Logic gate 104 comprises a p-channel transistor 102 and an n-channel transistor 100. P-channel transistor 102 has a source coupled to Vcc, a drain coupled to node Q 105, a gate coupled to node QB 106 and a substrate connected to Vcc. N-channel transistor 100 has a source 165 coupled to ground, a drain 160 coupled to Q node 105, a gate 162 coupled to QB node 106 and a substrate connection 190 also coupled to ground.
FIG. 1b is an illustration of a charged particle strike on a cross-section diagram of transistor 100. Transistor 100 comprises a drain 160, a source 165 and a gate 162. Gate oxide 163 separates gate 162 from drain 160, source 161 and substrate 190. As shown in FIG. 1b, the drain 160 is being struck by the charged particle (ion) 110 along the strike path 180. When the charged particle 110 passes though a semiconductor transistor 100 (potentially at relative velocities of 10,000 miles per hour or more), it ionizes atoms in the silicon leaving a wake of hole and electron pairs 120 behind. If it strikes the output diffusion of a complementary metal oxide semiconductor (CMOS) logic gate 104, as illustrated in FIG. 1a, all of those charge carriers are available as drift current 130 along strike path 180 if an electric field is present. If no electric field is present then the drift current 130 ultimately diffuses. If the output of the CMOS gate is not at the voltage of the surrounding material of the diffusion that is struck (for example, if N+ diffusion 160 is at Vcc and P-substrate 190 is at ground), then such an electric field exists and the current will pull diffusion 160 towards the voltage of the P-substrate 190 or ground.
In such an occurrence, there are two sources of current vying for control of the node Q: the CMOS p-channel device 102 (shown in FIG. 1a) that originally drove the node to the correct logic level and the pool of charge in the so-called “field funnel” 150 supplying drift current 130 in FIG. 1b. The larger current controls the node. If the strength of p-channel device 102 is large relative to the available drift current 130, then the node will barely move. If the strength of p-channel device 102 is small relative to the energy strike, then the drift current 130 in FIG. 1b controls and the node will move rapidly towards ground. When drift current 130 controls, it does so until all its charge dissipates, at which time the CMOS p-channel device 102 can restore the node to the correct value.
Unfortunately, it takes time for a small CMOS device to regain control against a high-energy strike. In the case, for example, of a victimized gate being part of the feedback path in a sequential (i.e. memory) element with the incorrect logic level propagating around the loop, the CMOS device gets shut off and is never able to make the needed correction and the memory element loses state. If the memory element controls something important, system or subsystem failure can result.
FIG. 2a is a simplified schematic diagram illustrating a particle strike on cross-coupled transistors. Transistors 102a, 102b, 100a and 100b form two logic gates like the logic gate 104 in FIG. 1a. In FIG. 2a, particle strike 210 is shown hitting the N+ region of n-channel transistor 100a. FIG. 2b illustrates the waveforms associated with this strike.
FIG. 2b is a diagram depicting the voltage waveforms 200 associated with a particle strike 210. The particular case shown is for a particle not quite capable of producing the critical charge required to flip the latch. At time T1, the particle hits and then node Q drops from its equilibrium value of Vcc very quickly due to the drift current in the field funnel 150 and QB rises due to the drop of Q. Meanwhile, transistor 102 pumps current into node Q slowing its fall. At T2, when all the charge in the field funnel 150 in FIG. 1b is exhausted, node Q quickly returns to its original equilibrium value of Vcc. Since the case depicted is close to the maximum amount of charge that the cell can withstand, the voltage on node Q approaches the trip point 230 at Vtrip. If the charged particle had created substantially more charge carriers than the transistor could have overcome, then node Q would have dropped to ground potential and QB would have risen to Vcc potential, and the latch would have flipped into the opposite state permanently.
SRAM in an FPGA may also be specified as CSRAM or USRAM. CSRAM is Configuration SRAM. This CSRAM is used to hold the configuration bits for the FPGA. It is physically spread out over the entire die and is interspersed with the rest of the FPGA circuitry. At least one of the two nodes in the static latch that make up the SRAM cell can be connected to the FPGA circuitry that controls it. When the contents of the CSRAM change, the logic function implemented by the FPGA changes. What is needed is a solution to insure the data integrity is maintained.
USRAM is the abbreviation for user SRAM. This is memory that is part of a user logic design and is concentrated inside a functional block dedicated to the purpose. What is needed is a solution to insure the data integrity of an USRAM is maintained.
In an SRAM based FPGA, there are a variety of separate elements that go into the making of a useful product. There are configuration memory bits in the CSRAM, which allow the user to impose his/her design on the uncommitted resources available. There are the combinational and sequential modules that do the user's logic. There are the configurable switches, signal lines, and buffers that allow the modules to be connected together. There are support circuits like clocks and other global signals like enables and resets, which allow the building of one or more subsystems in different time domains. There are blocks like the SRAM and DLL that allow the user access to more highly integrated functions than can be built out of an array of logic modules and interconnect.
Making each element radiation hardened is not practical due to area consideration since radiation hardened circuits tend to be rather large compared to non-radiation hardened circuits. What is needed is a prioritization of essential circuits to be hardened. Also, what is needed is a reliable radiation hardened FPGA that has a reasonable area that can be produced at a reasonable cost.
Moreover, what is needed is a way of providing a radiation-hardened SRAM based FPGA, which can easily be implemented using conventional CMOS processes, and which has performance and speed comparable to an SRAM based FPGA that has not been radiation-hardened.